Operands on the belt do not only come from immediate constants in the instruction stream or from results of computing operations. And the belt is also not the only place values can be written to. The most obvious place where values can go to and come from is main memory, accessible in a few different ways. There are also a few other sources and drains, like special registers.
Addresses are constructed from base dynamic pointers and static offsets (and sometimes additionally dynamic indices and static element size scales too). The base pointer can be an address in a belt operand, but most commonly address bases come from the value of some special register that is managed by hardware. The vast majority of code pointers is relative to the entry point of the current EBB. The vast majority of data accesses is relative to the current stack pointer, because most loads and stores come from the stack. There are a few more special registers, the global code register, the constant pool base register, fault vector base etc.
There are also a few optimizations, since protection regions are kept in special registers as upper and lower bounds, those upper and lower bounds can be used as address bases too, for smaller offsets.
Depending on the operation only a small subset of the registers are possible as base register. This means this base address register id can be encoded very densely into the operation.
For more look at the Registers.
Constants can be embedded immediately into the instruction stream in various ways. But those values have some size concerns, and somewhat connected to that, they can also only be scalar values.
For this reason there is a set of read-only registers that contain commonly used constants that usually are hard to encode efficiently. Things like [0 1 2 3] vectors, or if there are native floating point operations on the core, real numbers like, π, e, √2.
Those values are accessible with the rd operation.
This is an id for any special register, not an optimized encoding for special registers usable as an address base. Not all can be explicitly read with rd, not all can be explicitly written with wr though.
Streams provide cacheless bulk memory access for reading and writing.
To enable different speculative loads over parallel branches, it is possible to put a tag on a retire station on a load, and then later explicitly only take the value that you need with pickup and refuse the other.