# shiftluwv

From Mill Computing Wiki

speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes

**native on:** all

Unsigned bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening. Produces two result vectors.

**shiftluwv**(u x, *bit bits*) → u r_{0}, u r_{1}

**operands:**like Widenv XX:2X2X

Core | In Slots | Latencies |
---|---|---|

Tin | E0 | 2 2 |

Copper | E0 | 2 2 |

Silver | E0 E1 | 2 2 |

Gold | E0 E1 | 2 2 |

Decimal8 | E0 E1 | 2 2 |

Decimal16 | E0 E1 | 2 2 |

**shiftluwv**(u x, n bits) → u r_{0}, u r_{1}

**operands:**like Widenv XX:2X2X

Core | In Slots | Latencies |
---|---|---|

Tin | E0 | 2 2 |

Copper | E0 | 2 2 |

Silver | E0 E1 | 2 2 |

Gold | E0 E1 | 2 2 |

Decimal8 | E0 E1 | 2 2 |

Decimal16 | E0 E1 | 2 2 |

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable