shiftluw2
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
bitwise shift
shiftluw2(u op0, bit bit0) → u r0, u r1
operands: like Wideningv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
shiftluw2(u op0, u op1) → u r0, u r1
operands: like Wideningv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
