narrowux
From Mill Computing Wiki
realizing exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior
native on: all
Half the width of an unsigned integer value. Exception on overflow.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
narrowux(u op0, width width0) → u r0
operands: like Narrow [xx:½x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | |
Copper | E0 | |
Silver | E0 E1 E2 E3 | |
Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable