Difference between revisions of "Instruction Set/scratchf"

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(Created page with "{{DISPLAYTITLE:scratchf}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|reader...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#782|Tin]] || R0 R1 || 1
+
| [[Cores/Tin/Encoding#scratchf|Tin]] || R0 R1 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#782|Copper]] || R0 R1 || 1
+
| [[Cores/Copper/Encoding#scratchf|Copper]] || R0 R1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#782|Silver]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Silver/Encoding#scratchf|Silver]] || R0 R1 R2 R3 R4 R5 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#782|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 1
+
| [[Cores/Gold/Encoding#scratchf|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#782|Decimal8]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Decimal8/Encoding#scratchf|Decimal8]] || R0 R1 R2 R3 R4 R5 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#782|Decimal16]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Decimal16/Encoding#scratchf|Decimal16]] || R0 R1 R2 R3 R4 R5 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  reader block  compute phase   operation   in the logical value domain  

native on: all

allocate scratchpad frame


scratchf(scratch size)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 R4 R5 1
Gold R0 R1 R2 R3 R4 R5 R6 R7 1
Decimal8 R0 R1 R2 R3 R4 R5 1
Decimal16 R0 R1 R2 R3 R4 R5 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable