Difference between revisions of "Instruction Set/loadf"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#538|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#538|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#535|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#535|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 47:Line 47:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#542|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#542|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 61:Line 61:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#546|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#546|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 75:Line 75:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#543|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#543|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 90:Line 90:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#540|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#540|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 105:Line 105:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#544|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#544|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 121:Line 121:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#537|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#537|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 137:Line 137:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#545|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#545|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 151:Line 151:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#539|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#539|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 165:Line 165:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#536|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#536|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#541|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#541|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 195:Line 195:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#547|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#547|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 210:Line 210:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#548|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#548|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
  
Line 225:Line 225:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#549|Silver]] || F0 F1 F2 F3 || 3
+
| [[Cores/Silver/Encoding#loadf|Silver]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#549|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
+
| [[Cores/Gold/Encoding#loadf|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  flow stream  flow block  compute phase   operation   in the binary floating point value domain  

native on: Silver Gold

load from memory

loadf(base b, off o, s i, scale s, width w) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(base b, off o, s i, scale s, width w, lit delay) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(base b, off o, s i, scale s, width w, tag tag) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(base b, off o, width w) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(base b, off o, width w, lit delay) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(base b, off o, width w, tag tag) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, s i, scale s, width w) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, s i, scale s, width w, lit delay) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, s i, scale s, width w, tag tag) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, width w) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, width w, lit delay) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, off o, width w, tag tag) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, width w, memAttr m) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, width w, memAttr m, lit delay) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3

loadf(p b, width w, memAttr m, tag tag) → f r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Silver F0 F1 F2 F3 3
Gold F0 F1 F2 F3 F4 F5 F6 F7 3


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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