Difference between revisions of "Instruction Set/refuse"
From Mill Computing Wiki
(3 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{DISPLAYTITLE:refuse}} | {{DISPLAYTITLE:refuse}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|reader block]] [[Phasing| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|reader block]] [[Phasing|reader phase]] operation [[Domains|in the logical value domain]] <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
Line 14: | Line 14: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#refuse|Tin]] || R0 R1 || 1 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#refuse|Copper]] || R0 R1 || 1 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#refuse|Silver]] || R0 R1 R2 R3 || 1 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#refuse|Gold]] || R0 R1 || 1 |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
+ | |||
+ | |||
+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:00, 23 February 2021
reject a speculative load
refuse(tag tag)
operands: like NoArgs :[x]
Core | In Slots | Latencies |
---|---|---|
Tin | R0 R1 | 1 |
Copper | R0 R1 | 1 |
Silver | R0 R1 R2 R3 | 1 |
Gold | R0 R1 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable