shiftl

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speculable  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

aliases: shiftls shiftlu shiftls2 shiftlu2
native on: all

Bitwise left shift. The bit count by which to shift is an unsigned number. No overflows happen. Any bits moved beyond the width of the first argument just quietly disappear.


related operations: shiftrs, shiftru


shiftl(op x, bit bits) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0

shiftl(op x, n bits) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0


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