Difference between revisions of "Instruction Set/f2udn"
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Revision as of 06:59, 2 October 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain using modulo overflow behavior that produces condition codes
convert float to unsigned integer
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
