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realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   and rounds toward negative infinity

native on: none

Half the width of a decimal float value. Rounding towards negative infinity.

Can produce the IEEE 754 32bit decimal float interchange format.

This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.

narrowdn(d v1, d v2) → d r0

operands: like Narrowvd [DD:½D]

narrowdn(d op0, width width0) → d r0

operands: like Narrowd [dd:½d]

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable