f2sfixz

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using excepting overflow behavior   that produces condition codes and rounds toward zero

native on: Silver

convert float to signed integer

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f2sfixz(f op0) → f r0

operands: like Addf [ff:f]

Core	In Slots	Latencies
Silver	E0 E1	rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5

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