Difference between revisions of "Instruction Set/s2u"

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<code style="font-size:130%"><b style="color:#050">s2u</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">s2u</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
 
</div>
 
</div>
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#s2u|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#s2u|Tin]] || E0 ||  
 
|-
 
|-
| [[Cores/Copper/Encoding#s2u|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#s2u|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Silver/Encoding#s2u|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#s2u|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Gold/Encoding#s2u|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
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| [[Cores/Gold/Encoding#s2u|Gold]] || E0 ||  
|-
+
| [[Cores/Decimal8/Encoding#s2u|Decimal8]] || E0 E1 E2 E3 || 1
+
|-
+
| [[Cores/Decimal16/Encoding#s2u|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:06, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain   using modulo overflow behavior  

native on: all

Signed integer to unsigned integer.


s2u(op op0, width width0) → op r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable