Difference between revisions of "Instruction Set/rootu"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
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| [[Cores/Tin/Encoding#rootu|Tin]] || E0 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
+
| [[Cores/Tin/Encoding#rootu|Tin]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Copper/Encoding#rootu|Copper]] || E0 E1 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
+
| [[Cores/Copper/Encoding#rootu|Copper]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Silver/Encoding#rootu|Silver]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
+
| [[Cores/Silver/Encoding#rootu|Silver]] || E0 E1 E2 E3 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Gold/Encoding#rootu|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
+
| [[Cores/Gold/Encoding#rootu|Gold]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
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|-
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−
| [[Cores/Decimal8/Encoding#rootu|Decimal8]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
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−
|-
+
−
| [[Cores/Decimal16/Encoding#rootu|Decimal16]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:07, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: all

Unsigned integer square root. Helper operation for software square root implementation.

This operation creates a seed value for Newton-Rapheson, or other, iterative methods.

rootu(u x) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Copper E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Silver E0 E1 E2 E3 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Gold E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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