rdivu

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realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain  

native on: all

reciprocal divide


rdivu(u x) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Copper E0 E1 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Silver E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Decimal8 E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Decimal16 E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable