Difference between revisions of "Instruction Set/mask"

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----
 
----
<code style="font-size:130%"><b style="color:#050">mask</b>(<i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit0</span></i>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit1</span></i>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and scalarity (exu)">w</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">mask</b>(<i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit0</span></i>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit1</span></i>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">w</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
</div>
 
</div>
Line 21:Line 21:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#mask|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#mask|Tin]] || E0 ||  
 
|-
 
|-
| [[Cores/Copper/Encoding#mask|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#mask|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Silver/Encoding#mask|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#mask|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Gold/Encoding#mask|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#mask|Gold]] || E0 ||  
|-
+
| [[Cores/Decimal8/Encoding#mask|Decimal8]] || E0 E1 E2 E3 || 1
+
|-
+
| [[Cores/Decimal16/Encoding#mask|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
 
----
 
----
<code style="font-size:130%"><b style="color:#050">mask</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and scalarity (exu)">w</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">mask</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">w</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeMask|like Mask xX:X|Xx:x]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeMask|like Mask xX:X|Xx:x]]
 
</div>
 
</div>
Line 79:Line 75:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#mask|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#mask|Tin]] || E0 ||  
|-
+
| [[Cores/Copper/Encoding#mask|Copper]] || E0 E1 || 1
+
|-
+
| [[Cores/Silver/Encoding#mask|Silver]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
| [[Cores/Gold/Encoding#mask|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Copper/Encoding#mask|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Decimal8/Encoding#mask|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#mask|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#mask|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#mask|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:04, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Convert between bitmasks and bool vectors.

The lowest width bits of a bitmask become the element bool values of a new vector, or the bool element values of a vector become the new bits in a bitmask, depending on whether the input operand is a scalar or a vector.


mask(bit bit0, bit bit1, width w) → op r0

operands: like Identity [xx:x]

This doesn't work with vectors at all. It doesn't even have belt operands. It is rather a way to produce a class of often used constant values that usually would take a lot of space as a normal manifest constant.

The values produced by mask are bitmasks: A sequence of ones in an otherwise empty bitfield, or a sequence of zeros in an otherwise filled bitfield.

The two bit paramters are the start and stop bit indices, i.e. the greater value is the highest order bit that is part of the sequence, and the lower value is the highest order bit not part of the sequence anymore. When the greater value is first, it is a series of ones within zeros, when it is second, it is a series of zeros within ones.

Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

mask(op v, width w) → op r0

operands: like Mask xX:X|Xx:x

The width determines how many bits or elements are used from the operand. The bool vector conversion mask operation has one of the more complicated operand masks. This is because the direction of the conversion, vector to bitmask or vice versa, depends on the scalarity Metadata.
So from this perspective it isn't that complicated at all: bitmasks produce bool vectors, and bool vectors produce bitmasks.

bhwdqbvhvwvdvqv
b
h
w
d
q
bv
hv
wv
dv
qv


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable