Difference between revisions of "Instruction Set/f2ufexn"

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Latest revision as of 14:06, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using excepting overflow behavior   that produces condition codes and rounds toward negative infinity

native on: Silver

convert float to unsigned integer


f2ufexn(f op0) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5


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