Difference between revisions of "Instruction Set/addus"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:addus}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
Line 5:Line 5:
 
</div>
 
</div>
  
addition
+
Saturating unsigned integer addition.
 +
When a result value overflows for the width, it flats out at the biggest value.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addus</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addus</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>

Revision as of 10:19, 12 November 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using saturating overflow behavior   that produces condition codes

aliases: addusv
native on: all

Saturating unsigned integer addition. When a result value overflows for the width, it flats out at the biggest value.


addus(u x, u y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2

addus(u x, imm y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2