Difference between revisions of "Instruction Set/addswv"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:addswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
 
(3 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:addswv}}
 
{{DISPLAYTITLE:addswv}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
−
addition
+
Widening signed integer vector addition.
 +
If any of the result values in the vector overflows, the vector is widened as with [[Instruction_Set/widenuv|widenuv]].
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>
Line 14:Line 16:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#198|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#addswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#198|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#addswv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#198|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#addswv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#198|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#addswv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#198|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#addswv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#198|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#addswv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
  
Line 36:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#199|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#addswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#199|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#addswv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#199|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#addswv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#199|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#addswv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#199|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#addswv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#199|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#addswv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:30, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening signed integer vector addition. If any of the result values in the vector overflows, the vector is widened as with widenuv.

addswv(s x, s y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2

addswv(s x, imm y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/addswv&oldid=3964"