Difference between revisions of "Instruction Set/adddp"

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{{DISPLAYTITLE:adddp}}
 
{{DISPLAYTITLE:adddp}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward positive infinity]]<br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
</div>
 
</div>

Revision as of 18:51, 20 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   that produces condition codes and rounds toward positive infinity

native on: Decimal8 Decimal16

Decimal floating point add in current rounding towards positive infinity.


adddp(d x, d y) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
Decimal16 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5


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