Difference between revisions of "Cores/Tin"

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m (Protected "Cores/Tin": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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{{DISPLAYTITLE:Tin Core}}
 
{{DISPLAYTITLE:Tin Core}}
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<b>[[Cores]]:</b> [[Cores/Tin|Tin]]&nbsp;[[Cores/Copper|Copper]]&nbsp;[[Cores/Silver|Silver]]&nbsp;[[Cores/Gold|Gold]]&nbsp;[[Cores/Decimal8|Decimal8]]&nbsp;[[Cores/Decimal16|Decimal16]]&nbsp;
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<b>[[Cores]]:</b> [[Cores/Tin|Tin]]&nbsp;[[Cores/Copper|Copper]]&nbsp;[[Cores/Silver|Silver]]&nbsp;[[Cores/Gold|Gold]]&nbsp;
  
 
Tin is the smallest viable general purpose chip. It only has each one properly populated exu and flow slot, so instruction level parallelism is quite limited. It also doesn't support wider vector operands. It is extremely low power though, so it would lend itself to ultra-mobile devices or it could serve as an overblown micro controller.
 
Tin is the smallest viable general purpose chip. It only has each one properly populated exu and flow slot, so instruction level parallelism is quite limited. It also doesn't support wider vector operands. It is extremely low power though, so it would lend itself to ultra-mobile devices or it could serve as an overblown micro controller.
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<b>[[Belt]]</b>: 8&nbsp;&nbsp;<b>[[Decode#Morsel|Morsel]]</b>: 3bit&nbsp;&nbsp;<b>[[Operands|Scalar Width]]</b>: 64bit&nbsp;&nbsp;<b>[[Operands|Operand Maximum Size]]</b>: 8B&nbsp;&nbsp;
 
<b>[[Belt]]</b>: 8&nbsp;&nbsp;<b>[[Decode#Morsel|Morsel]]</b>: 3bit&nbsp;&nbsp;<b>[[Operands|Scalar Width]]</b>: 64bit&nbsp;&nbsp;<b>[[Operands|Operand Maximum Size]]</b>: 8B&nbsp;&nbsp;
  
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<b>[[Pipeline]]s</b>: 13&nbsp;&nbsp;<b>[[Retire Station]]s</b>: 8&nbsp;&nbsp;<b>[[Scratchpad]]</b>: 128B&nbsp;&nbsp;
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<b>[[Pipeline]]s</b>: 19&nbsp;&nbsp;<b>[[Retire Station]]s</b>: 8&nbsp;&nbsp;<b>[[Scratchpad]]</b>: 4096B&nbsp;&nbsp;
  
 
<b>[[Spiller|Spill Buffers]]</b>: 8&nbsp;&nbsp;<b>[[Spiller|Spiller Stack Size]]</b>: 16MB&nbsp;&nbsp;
 
<b>[[Spiller|Spill Buffers]]</b>: 8&nbsp;&nbsp;<b>[[Spiller|Spiller Stack Size]]</b>: 16MB&nbsp;&nbsp;
  
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<b>[[Memory#Instruction_Cache|iCache Line]]</b>: 16B&nbsp;&nbsp;
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<b>[[Memory#Instruction_Cache|iCache Line]]</b>: NoneB&nbsp;&nbsp;
  
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<b>2 reader slots</b>, 9bits wide&nbsp;&nbsp;&nbsp;<b>2 writer slots</b>, 6bits wide&nbsp;&nbsp;&nbsp;<b>1 pick slots</b>, 10bits wide&nbsp;&nbsp;&nbsp;
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<b>2 reader slots</b>, 17bits wide&nbsp;&nbsp;&nbsp;<b>2 writer slots</b>, 20bits wide&nbsp;&nbsp;&nbsp;<b>1 pick slots</b>, 11bits wide&nbsp;&nbsp;&nbsp;
  
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<b>exu slot 0</b>, 18bits wide, with functional units: [[Functional Unit#alu|alu]]&nbsp;[[Functional Unit#count|count]]&nbsp;[[Functional Unit#mul|mul]]&nbsp;[[Functional Unit#nope|nope]]&nbsp;[[Functional Unit#shift|shift]]&nbsp;[[Functional Unit#shuffle|shuffle]]&nbsp;
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<b>exu slot 0</b>, 19bits wide, with functional units: [[Functional Unit#alu|alu]]&nbsp;[[Functional Unit#count|count]]&nbsp;[[Functional Unit#mul|mul]]&nbsp;[[Functional Unit#NaR|NaR]]&nbsp;[[Functional Unit#nope|nope]]&nbsp;[[Functional Unit#shift|shift]]&nbsp;[[Functional Unit#shuffle|shuffle]]&nbsp;
  
 
<b>exu slot 1</b>, 7bits wide, with functional units: [[Functional Unit#cc|cc]]&nbsp;[[Functional Unit#exuArgs|exuArgs]]&nbsp;
 
<b>exu slot 1</b>, 7bits wide, with functional units: [[Functional Unit#cc|cc]]&nbsp;[[Functional Unit#exuArgs|exuArgs]]&nbsp;
  
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<b>flow slot 0</b>, 15bits wide, with functional units: [[Functional Unit#cache|cache]]&nbsp;[[Functional Unit#con|con]]&nbsp;[[Functional Unit#conform|conform]]&nbsp;[[Functional Unit#control|control]]&nbsp;[[Functional Unit#ls|ls]]&nbsp;[[Functional Unit#misc|misc]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
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<b>flow slot 0</b>, 18bits wide, with functional units: [[Functional Unit#boot|boot]]&nbsp;[[Functional Unit#cache|cache]]&nbsp;[[Functional Unit#con|con]]&nbsp;[[Functional Unit#conform|conform]]&nbsp;[[Functional Unit#control|control]]&nbsp;[[Functional Unit#ls|ls]]&nbsp;[[Functional Unit#misc|misc]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
  
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<b>flow slot 1</b>, 9bits wide, with functional units: [[Functional Unit#con|con]]&nbsp;[[Functional Unit#flowArgs|flowArgs]]&nbsp;
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<b>flow slot 1</b>, 8bits wide, with functional units: [[Functional Unit#flowArgs|flowArgs]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
  
  
  
 
[[Cores/Tin/Encoding|Operation Encoding]]
 
[[Cores/Tin/Encoding|Operation Encoding]]

Latest revision as of 14:14, 23 February 2021

Cores: Tin Copper Silver Gold 

Tin is the smallest viable general purpose chip. It only has each one properly populated exu and flow slot, so instruction level parallelism is quite limited. It also doesn't support wider vector operands. It is extremely low power though, so it would lend itself to ultra-mobile devices or it could serve as an overblown micro controller.


Belt: 8  Morsel: 3bit  Scalar Width: 64bit  Operand Maximum Size: 8B  

Pipelines: 19  Retire Stations: 8  Scratchpad: 4096B  

Spill Buffers: 8  Spiller Stack Size: 16MB  

iCache Line: NoneB  

2 reader slots, 17bits wide   2 writer slots, 20bits wide   1 pick slots, 11bits wide   

exu slot 0, 19bits wide, with functional units: alu count mul NaR nope shift shuffle 

exu slot 1, 7bits wide, with functional units: cc exuArgs 

flow slot 0, 18bits wide, with functional units: boot cache con conform control ls misc nopf 

flow slot 1, 8bits wide, with functional units: flowArgs nopf 


Operation Encoding

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