addss

From Mill Computing Wiki
Revision as of 06:56, 2 October 2014 by Shookie (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search
realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using saturating overflow behavior   that produces condition codes

aliases: addssv
native on: all

addition


addss(s x, s y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2

addss(s x, imm y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2