shiftlux
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior that produces condition codes
aliases: shiftluxv
native on: all
Unsigned bitwise left shift. Excepting. The bit count by which to shift is an unsigned number. Whenever a one gets moved out, an overflow NaR is produced.
shiftlux(u x, bit bits) → u r0
operands: like Shift [xi:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Copper | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Silver | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Gold | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Decimal8 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Decimal16 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
operands: like Shift [xi:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Copper | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Silver | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Gold | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Decimal8 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
| Decimal16 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
