shiftlsw

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realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening.


shiftlsw(s x, bit bits) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2

shiftlsw(s x, n bits) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable