add1u

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: all

Increment by one.

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add1u(u x, u y) → u r0

operands: like Identity [xx:x]

Core	In Slots	Latencies
Tin	E0	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
Copper	E0 E1	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
Silver	E0 E1 E2 E3	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
Gold	E0 E1 E2 E3 E4 E5 E6 E7	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
Decimal8	E0 E1 E2 E3	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
Decimal16	E0 E1 E2 E3	b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable