all

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realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

vector AND reduction

all(op v) → op r0

operands: like Leftv XX:i


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1
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