shiftlux
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior that produces condition codes
aliases: shiftlux2
native on: all
Unsigned bitwise left shift. Excepting. The bit count by which to shift is an unsigned number. Whenever a one gets moved out, an overflow NaR is produced.
shiftlux(u x, bit bits) → u r0
operands: like Shift [xi:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
operands: like Shift [xi:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
