subsw
From Mill Computing Wiki
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
subtraction
operands: like Widen xx:2x
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
operands: like Widen xx:2x
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable