Difference between revisions of "Instruction Set/f2uefxfz"

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Revision as of 06:58, 2 October 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using excepting overflow behavior   that produces condition codes

native on: Silver Gold

convert float to unsigned integer


f2uefxfz(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Gold E0 E1 E2 E3 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5