Difference between revisions of "Instruction Set/subsw"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:subsw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") |
(No difference) |
Revision as of 06:57, 2 October 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
subtraction
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
