Difference between revisions of "Instruction Set/muluwv"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:muluwv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") |
(No difference) |
Revision as of 06:57, 2 October 2014
realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
multiplication
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Copper | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Silver | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Gold | E0 E1 E2 E3 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal8 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal16 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
