Difference between revisions of "Instruction Set/subuwv"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:subuwv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") |
(No difference) |
Revision as of 06:56, 2 October 2014
realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
subtraction
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
subuwv(u x, imm y) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
