Difference between revisions of "Instruction Set/mulsfxn"
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{{DISPLAYTITLE:mulsfxn}} | {{DISPLAYTITLE:mulsfxn}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed fixed point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]]<br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed fixed point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | Signed Fixed Point multiply. Rounds towards negative infinity. | |
| + | Excepting. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">mulsfxn</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">dot</span></i>) → [[Domains#sf|sf]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">mulsfxn</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">dot</span></i>) → [[Domains#sf|sf]] r<sub>0</sub></code> | ||
Revision as of 18:51, 20 December 2014
realizing exu stream exu block compute phase operation in the signed fixed point value domain using excepting overflow behavior that produces condition codes and rounds toward negative infinity
native on: all
Signed Fixed Point multiply. Rounds towards negative infinity. Excepting.
mulsfxn(sf x, sf y, bit dot) → sf r0
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Copper | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Silver | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Gold | E0 E1 E2 E3 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal8 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal16 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
