Difference between revisions of "Instruction Set/shiftlsw"

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(Created page with "{{DISPLAYTITLE:shiftlsw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu blo...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#790|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#790|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#790|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#790|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#790|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#shiftlsw|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#790|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#shiftlsw|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#789|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#789|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#789|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#789|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#789|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#shiftlsw|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#789|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#shiftlsw|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

bitwise shift

shiftlsw(s x, bit bits) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2

shiftlsw(s x, n bits) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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