Difference between revisions of "Instruction Set/neqp"

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(Created page with "{{DISPLAYTITLE:neqp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#687|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#neqp|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#687|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#neqp|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#687|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#neqp|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#687|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#neqp|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#687|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#neqp|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#687|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#neqp|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">neqp</b>(<span style="color:#666">conditioncode</span>) &#8594; [[Domains#p|p]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">neqp</b>([[Condition_Code|<span style="color:#666">conditioncode</span>]]) &#8594; [[Domains#p|p]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeEqlp|like Eqlp pp:p]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeEqlp|like Eqlp pp:p]]
 
</div>
 
</div>
Line 37:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1165|Tin]] || e0 || 2
+
| [[Cores/Tin/Encoding#neqp|Tin]] || e0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1165|Copper]] || e0 || 2
+
| [[Cores/Copper/Encoding#neqp|Copper]] || e0 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1165|Silver]] || e0 || 2
+
| [[Cores/Silver/Encoding#neqp|Silver]] || e0 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1165|Gold]] || e0 || 2
+
| [[Cores/Gold/Encoding#neqp|Gold]] || e0 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1165|Decimal8]] || e0 || 2
+
| [[Cores/Decimal8/Encoding#neqp|Decimal8]] || e0 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1165|Decimal16]] || e0 || 2
+
| [[Cores/Decimal16/Encoding#neqp|Decimal16]] || e0 || 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the pointers value domain  

native on: all

not equal

neqp(p x, p y) → p r0

operands: like Eqlp pp:p


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2

neqp(conditioncode) → p r0

operands: like Eqlp pp:p


alternate encoding: skinny

Core In Slots Latencies
Tin e0 2
Copper e0 2
Silver e0 2
Gold e0 2
Decimal8 e0 2
Decimal16 e0 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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