Difference between revisions of "Instruction Set/gtr"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:gtr}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exuSkinny bl...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#gtr|Tin]] || e1 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#gtr|Copper]] || e1 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#gtr|Silver]] || e1 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#gtr|Gold]] || e1 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#gtr|Decimal8]] || e1 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#gtr|Decimal16]] || e1 || 1 |
|} | |} | ||
---- | ---- | ||
| − | <code style="font-size:130%"><b style="color:#050">gtr</b>(<span style="color:#666">conditioncode</span>) → [[Domains#op|op]] r<sub>0</sub></code> | + | <code style="font-size:130%"><b style="color:#050">gtr</b>([[Condition_Code|<span style="color:#666">conditioncode</span>]]) → [[Domains#op|op]] r<sub>0</sub></code> |
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]] | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]] | ||
</div> | </div> | ||
| + | Gets the greater than condition code of the ganged operation and puts it on the belt. | ||
| + | |||
| + | <b>related operations:</b> [[Instruction_Set/eql|eql]], [[Instruction_Set/neq|neq]], [[Instruction_Set/geq|geq]], [[Instruction_Set/lss|lss]], [[Instruction_Set/leq|leq]], [[Instruction_Set/carry|carry]], [[Instruction_Set/overflows|overflows]], [[Instruction_Set/fault|fault]] | ||
<br /> | <br /> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#gtr|Tin]] || E0 E1 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#gtr|Copper]] || E0 E1 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#gtr|Silver]] || E0 E1 E2 E3 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#gtr|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#gtr|Decimal8]] || E0 E1 E2 E3 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#gtr|Decimal16]] || E0 E1 E2 E3 || 1 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:37, 16 December 2014
realizing exu stream exuSkinny block compute phase operation in the logical value domain
native on: all
greater than
operands: like Identity [xx:x]
alternate encoding: skinny
| Core | In Slots | Latencies |
|---|---|---|
| Tin | e1 | 1 |
| Copper | e1 | 1 |
| Silver | e1 | 1 |
| Gold | e1 | 1 |
| Decimal8 | e1 | 1 |
| Decimal16 | e1 | 1 |
gtr(conditioncode) → op r0
operands: like Identity [xx:x]
Gets the greater than condition code of the ganged operation and puts it on the belt.
related operations: eql, neq, geq, lss, leq, carry, overflows, fault
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 E1 | 1 |
| Copper | E0 E1 | 1 |
| Silver | E0 E1 E2 E3 | 1 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
| Decimal8 | E0 E1 E2 E3 | 1 |
| Decimal16 | E0 E1 E2 E3 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
