Difference between revisions of "Instruction Set/lssdx"

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(Created page with "{{DISPLAYTITLE:lssdx}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Decimal8/Encoding#554|Decimal8]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5  
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| [[Cores/Decimal8/Encoding#lssdx|Decimal8]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5  
 
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| [[Cores/Decimal16/Encoding#554|Decimal16]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5  
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| [[Cores/Decimal16/Encoding#lssdx|Decimal16]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5  
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

less than

lssdx(d x, d y) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
Decimal16 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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