Difference between revisions of "Instruction Set/addp"

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addition
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Pointer addition. Protects the upper 4 reserved bits, can be scaled for indexing.
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<code style="font-size:130%"><b style="color:#050">addp</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale factor for indexes  
 
<code style="font-size:130%"><b style="color:#050">addp</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale factor for indexes  

Revision as of 18:47, 26 November 2014

realizing  exu stream  exu block  compute phase   operation   in the pointers value domain  

native on: all

Pointer addition. Protects the upper 4 reserved bits, can be scaled for indexing.


addp(p x, p y, scale s) → p r0

operands: like Addp [px:p]


Core In Slots Latencies
Tin E0 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Copper E0 E1 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Silver E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Decimal8 E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Decimal16 E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2

addp(p x, imm y, scale s) → p r0

operands: like Addp [px:p]


Core In Slots Latencies
Tin E0 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Copper E0 E1 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Silver E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Decimal8 E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
Decimal16 E0 E1 E2 E3 d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2