Difference between revisions of "Instruction Set/vec"

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(Created page with "{{DISPLAYTITLE:vec}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block&...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1107|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#vec|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1107|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#vec|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1107|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#vec|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1107|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#vec|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1107|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#vec|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1107|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#vec|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

vector constructor

vec(ops args) → op r0

operands: like Splat xx:X


encoding: vec(op op0) , vec(op op0, op op1)

Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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