Difference between revisions of "Instruction Set/shiftlswv"

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(Created page with "{{DISPLAYTITLE:shiftlswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bl...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#791|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftlswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#791|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftlswv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#791|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftlswv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#791|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftlswv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#791|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftlswv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#791|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftlswv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#792|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftlswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#792|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftlswv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#792|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftlswv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#792|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftlswv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#792|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftlswv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#792|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftlswv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

bitwise shift

shiftlswv(s x, bit bits) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2

shiftlswv(s x, n bits) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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