Difference between revisions of "Instruction Set/shuffle"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#shuffle|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#shuffle|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#shuffle|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#shuffle|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#shuffle|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#shuffle|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#shuffle|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#shuffle|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#shuffle|Decimal8]] || E0 E1 E2 E3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#shuffle|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:25, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Create a new vector where the elements are the values of the first operand vector and their respective positions in the second operand vector.

related operations: alternate, vec, inject, extract

shuffle(op vs, op positions) → op r0

operands: like Shuffle [xn:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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