Difference between revisions of "Instruction Set/orl"

From Mill Computing Wiki
Jump to: navigation, search
Line 16:Line 16:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#706|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#orl|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#706|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#orl|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#706|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#orl|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#706|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#orl|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#706|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#orl|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#706|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#orl|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#707|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#orl|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#707|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#orl|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#707|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#orl|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#707|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#orl|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#707|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#orl|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#707|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#orl|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

aliases: orls orlu
native on: all

Bitwise or.

orl(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

orl(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/orl&oldid=1803"