Difference between revisions of "Instruction Set/f2uefsz"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#415|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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| [[Cores/Silver/Encoding#f2uefsz|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|-
 
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| [[Cores/Gold/Encoding#415|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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| [[Cores/Gold/Encoding#f2uefsz|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
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|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using saturating overflow behavior   that produces condition codes

native on: Silver Gold

Exactly convert a binary floating point value to a unsigned integer, rounding toward zero and producing saturating result values.


f2uefsz(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Gold E0 E1 E2 E3 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable