Difference between revisions of "Instruction Set/addus"

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(Created page with "{{DISPLAYTITLE:addus}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
 
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{{DISPLAYTITLE:addus}}
 
{{DISPLAYTITLE:addus}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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'''aliases:''' addusv <br />
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'''aliases:''' addus2 <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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addition
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Saturating unsigned integer addition.
 +
When a result value overflows for the width, it flats out at the biggest value.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addus</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addus</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#203|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addus|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#203|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addus|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#203|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addus|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#203|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addus|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#203|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#203|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#202|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addus|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#202|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addus|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#202|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addus|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#202|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addus|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#202|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#202|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:13, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using saturating overflow behavior   that produces condition codes

aliases: addus2
native on: all

Saturating unsigned integer addition. When a result value overflows for the width, it flats out at the biggest value.

addus(u x, u y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

addus(u x, imm y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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