Difference between revisions of "Instruction Set/geq"

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(Created page with "{{DISPLAYTITLE:geq}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block&...")
 
 
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{{DISPLAYTITLE:geq}}
 
{{DISPLAYTITLE:geq}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
greater than or equal
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Integer greater than or equal comparison.
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All comparison operations produce 0 or 1 values of the operand width.
 +
 
 
----
 
----
<code style="font-size:130%"><b style="color:#050">geq</b>(<span style="color:#666">conditioncode</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">geq</b>([[Condition_Code|<span style="color:#666">conditioncode</span>]]) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
</div>
 
</div>
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Gets the equal or greater than condition code of the ganged operation and puts it on the belt.
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<b>related operations:</b> [[Instruction_Set/eql|eql]], [[Instruction_Set/neq|neq]], [[Instruction_Set/gtr|gtr]], [[Instruction_Set/lss|lss]], [[Instruction_Set/leq|leq]], [[Instruction_Set/carry|carry]], [[Instruction_Set/overflow|overflow]], [[Instruction_Set/fault|fault]]
 
<br />
 
<br />
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#449|Tin]] || E0 E1 || 1
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| [[Cores/Tin/Encoding#geq|Tin]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#449|Copper]] || E0 E1 || 1
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| [[Cores/Copper/Encoding#geq|Copper]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#449|Silver]] || E0 E1 E2 E3 || 1
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| [[Cores/Silver/Encoding#geq|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#449|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
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| [[Cores/Gold/Encoding#geq|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#449|Decimal8]] || E0 E1 E2 E3 || 1
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| [[Cores/Decimal8/Encoding#geq|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#449|Decimal16]] || E0 E1 E2 E3 || 1
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| [[Cores/Decimal16/Encoding#geq|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
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 +
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:29, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Integer greater than or equal comparison. All comparison operations produce 0 or 1 values of the operand width.


geq(conditioncode) → op r0

operands: like Identity [xx:x]

Gets the equal or greater than condition code of the ganged operation and puts it on the belt.

related operations: eql, neq, gtr, lss, leq, carry, overflow, fault

Core In Slots Latencies
Tin E0 E1 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable