Difference between revisions of "Instruction Set/u2sw"

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(Created page with "{{DISPLAYTITLE:u2sw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
 
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{{DISPLAYTITLE:u2sw}}
 
{{DISPLAYTITLE:u2sw}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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convert unsigned to signed
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Unsigned integer to signed integer. Widening.
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">u2sw</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">u2sw</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#895|Tin]] || E0 || 1
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| [[Cores/Tin/Encoding#u2sw|Tin]] || E0 || 1
 
|-
 
|-
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| [[Cores/Copper/Encoding#895|Copper]] || E0 E1 || 1
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| [[Cores/Copper/Encoding#u2sw|Copper]] || E0 || 1
 
|-
 
|-
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| [[Cores/Silver/Encoding#895|Silver]] || E0 E1 E2 E3 || 1
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| [[Cores/Silver/Encoding#u2sw|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
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| [[Cores/Gold/Encoding#895|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
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| [[Cores/Gold/Encoding#u2sw|Gold]] || E0 || 1
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|-
+
−
| [[Cores/Decimal8/Encoding#895|Decimal8]] || E0 E1 E2 E3 || 1
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−
|-
+
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| [[Cores/Decimal16/Encoding#895|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:03, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain   using widening overflow behavior  

native on: all

Unsigned integer to signed integer. Widening.

u2sw(op x) → op r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 E1 E2 E3 1
Gold E0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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