Difference between revisions of "Instruction Set/addsx"

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(Created page with "{{DISPLAYTITLE:addsx}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
 
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{{DISPLAYTITLE:addsx}}
 
{{DISPLAYTITLE:addsx}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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'''aliases:''' addsxv <br />
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'''aliases:''' addsx2 <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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addition
+
Excepting signed integer add.
 +
Overflow or underflow produces a [[NaR]].
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addsx</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addsx</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#200|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addsx|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#200|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addsx|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#200|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addsx|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#200|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addsx|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#200|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#200|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#201|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addsx|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#201|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addsx|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#201|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addsx|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#201|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addsx|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#201|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#201|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:04, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using excepting overflow behavior   that produces condition codes

aliases: addsx2
native on: all

Excepting signed integer add. Overflow or underflow produces a NaR.

addsx(s x, s y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

addsx(s x, imm y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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