Difference between revisions of "Instruction Set/narrow"

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(Created page with "{{DISPLAYTITLE:narrow}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
m (Protected "Instruction Set/narrow": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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</div>
 
</div>
  
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narrow scalar to half width
+
Half the width of an integer value.
 +
 
 +
This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit.
 +
Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so.
 +
If narrowing should prove a big bottleneck this can be revisited.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">narrow</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">narrow</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#640|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#narrow|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#640|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#narrow|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#640|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#narrow|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#640|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#narrow|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#640|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#narrow|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#640|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#narrow|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#639|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#narrow|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#639|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#narrow|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#639|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#narrow|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#639|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#narrow|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#639|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#narrow|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#639|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#narrow|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 01:31, 3 January 2015

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: narrows narrowu
native on: all

Half the width of an integer value.

This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.

narrow(op v) → op r0

operands: like Narrow [xx:½x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

narrow(op v1, op v2) → op r0

operands: like Narrowv [XX:½x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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