Difference between revisions of "Instruction Set/f2udxz"
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(Created page with "{{DISPLAYTITLE:f2udxz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") | |||
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{{DISPLAYTITLE:f2udxz}} | {{DISPLAYTITLE:f2udxz}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br /> |
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | '''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | ||
</div> | </div> | ||
| − | convert | + | Inexactly convert a decimal floating point value to a unsigned integer, rounding toward zero and producing [[NaR]]s on overflow. |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">f2udxz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">f2udxz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#f2udxz|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#f2udxz|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|} | |} | ||
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| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:26, 9 February 2015
speculable exu stream exu block compute phase operation in the decimal floating point value domain using excepting overflow behavior that produces condition codes and rounds toward zero
Inexactly convert a decimal floating point value to a unsigned integer, rounding toward zero and producing NaRs on overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
