Difference between revisions of "Instruction Set/store"

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(Created page with "{{DISPLAYTITLE:store}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow bloc...")
 
 
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</div>
 
</div>
  
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store to memory
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Take a value from the belt and store it to the computed address.
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----
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<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Sources#base|base]]</span> <span title="base special register">b</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">o</span></i>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from opsWindow">i</span>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale factor
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            for indexes in load/store/lea">s</span></i>, <span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">v</span>)</code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
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</div>
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<br />
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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Stores always write into the top level data cache, i.e. they are only reflected in main memory after travelling down the cache hierarchy, unless other behavior is requested with special attributes.
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
 
−
|-
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The addressing modes are the same as for loads. The general formula for computing addresses is
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| [[Cores/Tin/Encoding#828|Tin]] || F0 || 1
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<code>base+offset+(scale*index)</code>.<br />
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|-
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Base can come from a number of special [[Registers]] or the belt. Offset is always an inline constant. Those two are always present, although a zero offset doesn't take any space at all.<br />
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| [[Cores/Copper/Encoding#828|Copper]] || F0 F1 || 1
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Scale and index are optional and alway appear together. The scale is a compile time constant, the index is always from the belt.
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|-
+
 
−
| [[Cores/Silver/Encoding#828|Silver]] || F0 F1 F2 F3 || 1
+
The width and scalarity of the value to store are determined from the metadata of the belt item that is getting stored. No need for any parameters or separate operations.
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|-
+
 
−
| [[Cores/Gold/Encoding#828|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
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<b>related operations:</b>  [[Instruction_Set/load|load]], [[Instruction_Set/storef|storef]], [[Instruction_Set/stored|stored]]
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|-
+
−
| [[Cores/Decimal8/Encoding#828|Decimal8]] || F0 F1 F2 F3 || 1
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−
|-
+
−
| [[Cores/Decimal16/Encoding#828|Decimal16]] || F0 F1 F2 F3 || 1
+
−
|}
+
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Sources#base|base]]</span> <span title="base special register">b</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">o</span></i>, <span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">v</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">base0</span>, <span style="color:#009">[[Sources#base|base]]</span> <span title="base special register">op0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">off0</span></i>)</code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeStore|like Store px:]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#829|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#829|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#829|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#829|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#829|Decimal8]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#829|Decimal16]] || F0 F1 F2 F3 || 1
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">b</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">o</span></i>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from opsWindow">i</span>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale
+
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">op0</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from opsWindow">op1</span>, <i><span style="color:#009">[[Immediates#memAttr|memAttr]]</span> <span title="special load/store  
−
            factor for indexes in load/store/lea">s</span></i>, <span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">v</span>)</code>
+
            behaviors">memAttr0</span></i>)</code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeStore|like Store px:]]
 
</div>
 
</div>
 
<br />
 
<br />
Line 60:Line 45:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#827|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#827|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#827|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#827|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#827|Decimal8]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#827|Decimal16]] || F0 F1 F2 F3 || 1
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">b</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">o</span></i>, <span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">v</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">op0</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from opsWindow">op1</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">off0</span></i>)</code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeStore|like Store px:]]
 
</div>
 
</div>
 
<br />
 
<br />
Line 82:Line 63:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#826|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#826|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#826|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#826|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#826|Decimal8]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#826|Decimal16]] || F0 F1 F2 F3 || 1
+
 
|}
 
|}
  
−
----
 
−
<code style="font-size:130%"><b style="color:#050">store</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">b</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="late-evaluated operand from belt">v</span>, <i><span style="color:#009">[[Immediates#memAttr|memAttr]]</span> <span title="special load/store
 
−
            behaviors">m</span></i>)</code>
 
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
−
</div>
 
−
<br />
 
  
−
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
+
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#825|Tin]] || F0 || 1
+
−
|-
+
−
| [[Cores/Copper/Encoding#825|Copper]] || F0 F1 || 1
+
−
|-
+
−
| [[Cores/Silver/Encoding#825|Silver]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Gold/Encoding#825|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#825|Decimal8]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#825|Decimal16]] || F0 F1 F2 F3 || 1
+
−
|}
+

Latest revision as of 14:00, 23 February 2021

realizing  flow stream  flow block  writer phase   operation   in the logical value domain  

native on: all

Take a value from the belt and store it to the computed address.

Stores always write into the top level data cache, i.e. they are only reflected in main memory after travelling down the cache hierarchy, unless other behavior is requested with special attributes.

The addressing modes are the same as for loads. The general formula for computing addresses is base+offset+(scale*index).
Base can come from a number of special Registers or the belt. Offset is always an inline constant. Those two are always present, although a zero offset doesn't take any space at all.
Scale and index are optional and alway appear together. The scale is a compile time constant, the index is always from the belt.

The width and scalarity of the value to store are determined from the metadata of the belt item that is getting stored. No need for any parameters or separate operations.

related operations: load, storef, stored

store(op base0, base op0, off off0)

operands: like Store px:


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1

store(op op0, op op1, memAttr memAttr0)

operands: like Store px:


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1

store(op op0, op op1, off off0)

operands: like Store px:


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/store&oldid=4665"