Difference between revisions of "Instruction Set/shiftlswv"

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(Created page with "{{DISPLAYTITLE:shiftlswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bl...")
 
 
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{{DISPLAYTITLE:shiftlswv}}
 
{{DISPLAYTITLE:shiftlswv}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
−
bitwise shift
+
Signed bitwise vector left shift. Widening.
 +
The bit count by which to shift is an unsigned number.
 +
The higher order bits get sign extended in the widening.
 +
Produces two result vectors.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">shiftlswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>
 
<code style="font-size:130%"><b style="color:#050">shiftlswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#791|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftlswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#791|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftlswv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#791|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftlswv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#791|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftlswv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#791|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftlswv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#791|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftlswv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#792|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftlswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#792|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftlswv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#792|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftlswv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#792|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftlswv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#792|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftlswv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#792|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftlswv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:24, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening. Produces two result vectors.

shiftlswv(s x, bit bits) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2

shiftlswv(s x, n bits) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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